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low skew, 1-to-6, differential-to- lvds fanout buffer ICS854S006I data sheet ics854s006agi revision b january 18, 2010 1 ? 2010 integrated device technology, inc. g eneral d escription the ics85 4s006i is a low skew, high perfor- mance 1-to-6 differential-to-lvds f anout buffer. the clk, nclk pair can accept most standard dif- ferential input levels. the ics85 4s006i is charac- terized to operate from either a 2.5v or a 3.3v power supply. guaranteed output skew characteristics make the ics85 4s006i ideal for those clock distribution applications demanding well defined performance and repeatability. f eatures ? six differential lvds outputs ? one differential clock input pair ? clk, nclk pair can accept the following differential input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? maximum output frequency: 1.7ghz ? translates any single ended input signal to lvds levels with resistor bias on nclk input ? output skew: 55ps (maximum) ? propagation delay: 850ps (maximum) ? additive phase jitter, rms: 0.067ps (typical) ? full 3.3v or 2.5v power supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages b lock d iagram p in a ssignment hiperclocks? ic s q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 clk nclk pullup pulldown ICS854S006I 24-lead tssop 4.40mm x 7.8mm x 0.925mm package body g package top view 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nclk clk v dd v ddo q0 nq0 gnd q1 nq1 v ddo q2 nq2 gnd gnd v dd v ddo nq5 q5 gnd nq4 q4 v ddo nq3 q3
ics854s006agi revision b january 18, 2010 2 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k t able 3. c lock i nput f unction t able r e b m u ne m a ne p y tn o i t p i r c s e d 1k l c nt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 2k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 2 2 , 3v d d r e w o p. s n i p y l p p u s e v i t i s o p 1 2 , 5 1 , 0 1 , 4v o d d r e w o p. s n i p y l p p u s t u p t u o 6 , 50 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 2 , 8 1 , 7d n gr e w o p. d n u o r g y l p p u s r e w o p 9 , 81 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 2 1 , 1 12 q n , 2 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 4 1 , 3 13 q n , 3 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 7 1 , 6 14 q n , 4 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 15 q n , 5 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p k l ck l c n5 q : 0 q5 q n : 0 q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i . " s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w " , n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n
ics854s006agi revision b january 18, 2010 3 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, i o (lvds) contin uous current 10ma surge current 15ma package thermal impedance, ja 70c/w (0 mps) storage temperature, t stg -65c to 150c (junction-to-ambient) note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v dd = v ddo = 3.3v5% or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 5 5a m i o d d t n e r r u c y l p p u s t u p t u o 5 0 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c v d d v = n i v 5 6 4 . 3 = v 5 2 6 . 2 r o 0 1a k l c n v d d , v 5 2 6 . 2 r o v 5 6 4 . 3 = v n i v 0 = 0 5 1a i l i t n e r r u c w o l t u p n i k l c v d d v = n i v 5 6 4 . 3 = v 5 2 6 . 2 r o 0 5 1 -a k l c n v d d , v 5 2 6 . 2 r o v 5 6 4 . 3 = v n i v 0 = 0 1 -a v p p 1 e t o n ; e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 -v v : 1 e t o n l i v 3 . 0 - n a h t s s e l e b t o n d l u o h s v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . t able 4b. p ower s upply dc c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 25 . 25 2 6 . 2v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 5 5a m i o d d t n e r r u c y l p p u s t u p t u o 2 0 1a m
ics854s006agi revision b january 18, 2010 4 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer t able 4e. lvds dc c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 5 0 35 0 5v m v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 1 . 15 4 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m . n o i t a m r o f n i t u p t u o r o f n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p o t r e f e r e s a e l p : e t o n . c e p s t e g r a t n g i s e d a s i e u l a v m u m i x a m : e t o n t able 4d. lvds dc c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 6 2 36 2 5v m v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 8 2 . 14 4 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m . n o i t a m r o f n i t u p t u o r o f n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p o t r e f e r e s a e l p : e t o n t able 5a. ac c haracteristics , v dd = v ddo = 3.3v 5%, t a = -40c to 85c t able 5b. ac c haracteristics , v dd = v ddo = 2.5v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 7 . 1z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p 0 0 30 0 8s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 5 5s p t t i j , r e t t i j e s a h p e v i t i d d a r e f f u b e s a h p e v i t i d d a o t r e f e r ; s m r n o i t c e s r e t t i j , z h m 8 0 . 2 2 6 z h m 0 2 ? z h k 2 1 : e g n a r n o i t a r g e t n i 7 6 0 . 0s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 50 5 2s p c d oe l c y c y t u d t u p t u o z h g 2 . 17 43 5% . a 5 e l b a t e e s , s e t o n r o f l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 7 . 1z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p 0 0 30 5 8s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 5 5s p t t i j , r e t t i j e s a h p e v i t i d d a r e f f u b e s a h p e v i t i d d a o t r e f e r ; s m r n o i t c e s r e t t i j , z h m 8 0 . 2 2 6 z h m 0 2 ? z h k 2 1 : e g n a r n o i t a r g e t n i 7 6 0 . 0s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 50 5 2s p c d oe l c y c y t u d t u p t u o z h g 2 . 17 43 5% d e h s i l b a t s e s i h c i h w , e g n a r e r u t a r e p m e t g n i t a r e p o t n e i b m a d e i f i c e p s e h t r e v o d e e t n a r a u g e r a s r e t e m a r a p l a c i r t c e l e : e t o n t e e m l l i w e c i v e d e h t . m p f l 0 0 5 n a h t r e t a e r g w o l f r i a e s r e v s n a r t d e n i a t n i a m h t i w t e k c o s t s e t a n i d e t n u o m s i e c i v e d e h t n e h w . s n o i t i d n o c e s e h t r e d n u d e h c a e r n e e b s a h m u i r b i l i u q e l a m r e h t r e t f a s n o i t a c i f i c e p s . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a m o r f d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
ics854s006agi revision b january 18, 2010 5 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer a dditive p hase j itter input/output additive phase jitter @ 622.08mhz (12khz to 20mhz) = 0.067ps (typical) the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
ics854s006agi revision b january 18, 2010 6 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer p arameter m easurement i nformation v cmr cross points v pp gnd nclk v dd clk t sk(o) nqx qx nqy qy t pd nclk q0:q5 nq0:nq5 clk d ifferential i nput l evel 2.5v c ore /2.5v o utput l oad ac t est c ircuit 3.3v c ore /3.3v o utput l oad ac t est c ircuit o utput s kew o utput r ise /f all t ime p ropagation d elay scope qx nqx lv d s 3.3v5% power supply +? float gnd scope qx nqx lv d s 2.5v5% power supply +? float gnd v dd, v ddo v dd, v ddo 20% 80% 80% 20% t r t f v od q0:q5 nq0:nq5
ics854s006agi revision b january 18, 2010 7 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer t pw t period t pw t period odc = x 100% q0:q5 nq0:nq5 d ifferential o utput v oltage s etup o ffset v oltage s etup o utput d uty c ycle /p ulse w idth /p eriod ? ? ? 100 out out lvds dc input v od / v od v dd out out lvds dc input ? ? ? v os / v os v dd p arameter m easurement i nformation , continued
ics854s006agi revision b january 18, 2010 8 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. o utputs : lvds o utputs all unused lvds output pairs can be either left floating or terminated with 100 across. if they are left floating, we recommend that there is no trace attached. r ecommendations for u nused o utput p ins v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd
ics854s006agi revision b january 18, 2010 9 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer f igure 2c. clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 2b. clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 2d. clk/nclk i nput d riven by a 3.3v lvds d river d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples f igure 2a. clk/nclk i nput d riven by an idt o pen e mitter lvhstl d river only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. f igure 2e. clk/nclk i nput d riven by a 3.3v hcsl d river f igure 2f. clk/nclk i nput d riven by a 2.5v sstl d river r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver differential input clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 clk nclk 3.3v 3.3v lvpecl differential input 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50 hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 zo = 50 differential input r1 50 r2 50 *optional ? r3 and r4 can be 0 clk nclk differential input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics854s006agi revision b january 18, 2010 10 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer 3.3v, 2.5v lvds d river t ermination a general lvds interface is shown in figure 3. in a 100 differential transmission line environment, lvds drivers require a matched load termination of 100 across near f igure 3. t ypical lvds d river t ermination the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 2.5v or 3.3v + - vdd 100 ohm differential transmission line r1 100 lvds_driv er
ics854s006agi revision b january 18, 2010 11 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS854S006I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854S006I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * i dd_max = 3.465v * 55ma = 190.575mw ? power (outputs) max = v ddo_max * i ddo_max = 3.465v * 105ma = 363.825mw total power _max = 190.575mw + 363.825mw = 554.4mw 2. junction temperature. junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 70c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.554w * 70c/w = 123.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 24-l ead tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 70c/w 65c/w 62c/w
ics854s006agi revision b january 18, 2010 12 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer r eliability i nformation t ransistor c ount the transistor count for ICS854S006I is: 293 t able 7. ja vs . a ir f low t able for 24 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 70c/w 65c/w 62c/w p ackage o utline - g s uffix for 24 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n4 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 7 . 70 9 . 7 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0 p ackage o utline & d imensions
ics854s006agi revision b january 18, 2010 13 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer t able 9. o rdering i nformation while the information presented herein has been checked for both accur acy and reliability, integrate d device t echnology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt prod uct for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i g a 6 0 0 s 4 5 8i g a 6 0 0 s 4 5 8 s c ip o s s t d a e l 4 2e b u tc 5 8 o t c 0 4 - t i g a 6 0 0 s 4 5 8i g a 6 0 0 s 4 5 8 s c ip o s s t d a e l 4 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i g a 6 0 0 s 4 5 8l i a 6 0 0 s 4 5 8 s c ip o s s t " e e r f - d a e l " d a e l 4 2e b u tc 5 8 o t c 0 4 - t f l i g a 6 0 0 s 4 5 8l i a 6 0 0 s 4 5 8 s c ip o s s t " e e r f - d a e l " d a e l 4 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
ics854s006agi revision b january 18, 2010 14 ? 2010 integrated device technology, inc. ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a e 4 t , d 4 t 9 t 4 3 1 v d e g n a h c - e l b a t s c i t s i r e t c a r a h c c d s d v l d o . v m o t v m o r f s t i n u . n m u l o c r e d r o / t r a p m o r f x i f e r p " s c i " d e t e l e d - e l b a t n o i t a m r o f n i g n i r e d r o . r e t o o f / r e d a e h f o e l y t s d e g n a h c 9 0 / 0 2 / 7 b 1 t c 4 t b 5 t , a 5 t 1 2 3 4 9 . " n w o d l l u p " o t k l c n d n a " p u l l u p " o t k l c d e g n a h c - m a r g a i d k c o l b . m a r g a i d k c o l b t c e l f e r o t " e p y t " k l c n d n a k l c d e g n a h c - s n o i t p i r c s e d n i p i - e l b a t s c i t s i r e t c a r a h c c d l a i t n e r e f f i d h i a u 0 5 1 m o r f s l e v e l k l c d e g n a h c , s r e t e m a r a p . x a m a u 0 5 1 o t . x a m a u 5 m o r f s l e v e l k l c n ; . x a m a u 0 1 o t . x a m i l i m o r f s l e v e l k l c n ; . n i m a u 0 5 1 - o t . n i m a u 5 - m o r f s l e v e l k l c d e g n a h c , s r e t e m a r a p . n i m a u 0 1 - o t . n i m a u 0 5 1 - . e t o n l a m r e h t d e d d a d e t a d p u e c a f r e t n i t u p n i k c o l c l a i t n e r e f f i d . n o i t c e s 0 1 / 8 1 / 1
sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt techical support netcom@idt.com +480-763-2056 6024 silver creek valley road san jose, ca 95138 ICS854S006I data sheet low skew, 1-to-6, differential-to-lvds fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performace, is subject to change without notice. performance s pecifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the in formation contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of idt?s products for any particular purpose, a n implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device techology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used her ein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. www.idt.com

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